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ISL8106
Data Sheet November 10, 2006 FN9283.1
Wide VIN, 7V to 25V, Single-Phase PWM Controller with Integrated MOSFET Drivers
The ISL8106 is a Single-Phase Synchronous-Buck PWM Controller with a input voltage range of +7.0V to +25.0V featuring Intersil's Robust Ripple Regulator (R3) technology that delivers exceptional dynamic response to input voltage and output load transients. Integrated MOSFET drivers, 5V LDO, and bootstrap diode result in fewer components and smaller implementation area for power supply systems. The ISL8106 features a 1.5ms digital soft-start and can be started into a pre-biased output voltage. A resistor divider is used to program the output voltage setpoint. The ISL8106 can be configured to operate in forced-continuousconduction-mode (FCCM) or in diode-emulation-mode (DEM), which improves light-load efficiency. In FCCM the controller always operates as a synchronous rectifier, switching the bottom-side MOSFET regardless of the output load. With DEM enabled, the bottom-side MOSFET is disabled preventing negative current flow from the output inductor during low load operation. This makes the ISL8106 an excellent choice for all "green" applications. An audio filter prevents the PWM switching frequency from entering the audible spectrum due to extremely light load while in DEM. A PGOOD pin featuring a unique fault-identification capability significantly reduces system trouble-shooting time and effort. The pull-down resistance of the PGOOD pin is 30 for an overcurrent fault, 60 for an overvoltage fault, or 90 for either an undervoltage fault or during soft-start. Overcurrent protection is accomplished by measuring the voltage drop across the rDS(ON) of the bottom-side MOSFET. A single resistor programs the overcurrent and short-circuit points. Overvoltage and undervoltage protection is monitored at the FB voltage feedback pin.
Features
* Wide input voltage range: +7.0V to +25.0V * High performance R3 technology delivers extremely fast transient response * +0.6V Internal Reference - 0.6% tolerance over the commercial temperature Range (0C to +70C) - 1.0% tolerance over the industrial temperature range (-40C to +85C) * Output voltage range: +0.6V to VCC-0.3V * Selectable forced continuous conduction mode or diode emulation mode * Integrated MOSFET drivers with shoot-through protection * External type-two loop compensation * Internal 5V low-dropout regulator with Integrated bootstrap diode * Programmable PWM frequency: 200kHz to 600kHz * PWM minimum frequency above audible spectrum * Internal digital soft-start with prebiased startup capability * Power good monitor with fault identification by PGOOD pull down resistance * Lossless, programmable overcurrent protection - Uses bottom-side MOSFET's rDS(ON) * Undervoltage protection, soft crowbar overvoltage protection and over-temperature protection * Pb-free plus anneal available (RoHS compliant)
Applications
* Telecom/datacom applications * Industrial applications * Distributed DC/DC power architecture * Point-of-load modules
Pinout
16 LD QFN (4mm x 4mm) TOP VIEW
PGOOD TGATE 14 BOOT 13 12 PVCC 11 BGATE GND FCCM EN 3 4 5 COMP 6 FB 7 FSET 8 VO 10 PGND 9 BSOC
16 VIN VCC 1 2
15
LX
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL8106 Ordering Information
PART NUMBER ISL8106CRZ* ISL8106IRZ* ISL8106EVAL1Z PART MARKING 8106CRZ 8106IRZ Evaluation Board TEMP (C) 0 to +70 -40 to +85 PACKAGE 16 Ld 4x4 QFN 16 Ld 4x4 QFN PKG. DWG. # L16.4x4 L16.4x4
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Typical Application
VIN +7V TO +25V PGOOD
RPGOOD
PGOOD
VIN BOOT CBOOT QTS
LOUT
CIN
PVCC RVCC VCC CPVCC CVCC GND
TGATE LX BSOC RBSOC
VOUT COUT
ISL8106
BGATE QBS
FCCM EN RCOMP COMP
PGND
FSET CCOMP1 FB CCOMP2 VO RFSET CFSET
RBOT
RTOP
2
FN9283.1 November 10, 2006
Block Diagram
VIN VO GND PACKAGE BOTTOM LDO PWM FREQUENCY CONTROL
FSET
VCC VREF
EN
gmVIN
VW
+ -
+
R PWM Q S
-
OVP
UVP
+
EA FB COMP BSOC DRIVER POR DIGITAL SOFT-START PWM CONTROL LX SHOOT THROUGH PROTECTION PVCC TGATE
-
OCP
PGOOD FCCM
+
IOC
30
90
-
- +
gmVO
+ -
CR
VCOMP
+
BOOT
60
DRIVER
150OT PGND
FN9283.1 November 10, 2006
-
+
VR
-
ISL8106
BGATE
+ -
+
-
3
ISL8106
Absolute Voltage Ratings
BSOC, VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VCC, PGOOD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V PVCC to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V GND to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V EN, FCCM. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V LX to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V . . . . . . . . . . . . . . . . . . . . . . . . . . (<100ns Pulse Width, 10J) -5.0V BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V BOOT to LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V TGATE . . . . . . . . . . . . . . . . . . . . . . .(DC) -0.3V to LX, BOOT +0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . (<200ns Pulse Width, 20J) -4.0V BGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . (<100ns Pulse Width, 4J) -2.0V ESD Classification . . . . . . . . . . . . . . . . . . . . . .Level 1 (HBM = 2kV)
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) QFN Package . . . . . . . . . . . . . . . . . . . 48 11.5 Junction Temperature Range . . . . . . . . . . . . . . . . . -55C to +150C Operating Temperature Range ISL8106CRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C ISL8106IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature . . . . . . . . . . . . . . . . . . . . (soldering, 10s)+300C
Recommended Operating Conditions
Ambient Temperature Range (ISL8106C) . . . . . . . . . . 0C to +70C Ambient Temperature Range (ISL8106I) . . . . . . . . . -40C to +85C Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . 7V to 25V
CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. Parameters are Guaranteed by Design.
Electrical Specifications
PARAMETER VIN VIN Voltage Range VIN Input Bias Current VIN Shutdown Current VCC LDO VCC Output Voltage Range VCC POR THRESHOLD
Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process, temperature, and line operating conditions. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VIN IVIN ISHDN EN and FCCM = 5V, FB = 0.65V, VIN = 7V to 25V EN = GND, VIN = 25V
7.0 2.2 0.1
25.0 3.0 1.0
V mA A
VCC
VIN = 7V to 25V, ILDO = 0mA to 80mA
4.75
5.00
5.25
V
Rising VCC POR Threshold Voltage
VCCTHR V
ISL8106CRZ ISL8106IRZ
4.35 4.33 4.10 4.08
4.45 4.45 4.20 4.20
4.55 4.55 4.30 4.30
V V V V
Falling VCC POR Threshold Voltage CONTROL INPUTS EN High Threshold Voltage EN Low Threshold Voltage FCCM High Threshold Voltage FCCM Low Threshold Voltage EN Leakage Current
CCTHF
ISL8106CRZ ISL8106IRZ
VENTHR VENTHF VFCCMTHR VFCCMTHF IENL IENH EN = 0V EN = 5.0V FCCM = 0V FCCM = 5.0V
2.0 0.5 2.0 1.0 <0.1 20 <0.1 2.0 1.0 1.0
V V V V A A A A
FCCM Leakage Current REFERENCE Reference Voltage Voltage Regulation Accuracy
IFCCML IFCCMH
VREF VREG ISL8106CRZ ISL8106IRZ -0.6 -1.0
0.6 +0.6 +1.0
V % %
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ISL8106
Electrical Specifications
PARAMETER PWM FOSC Frequency Range FAUDIO FCCM = 5V FCCM = GND; ISL8106CRZ FCCM = GND; ISL8106IRZ Frequency-Set Accuracy VO Range VO Input Leakage Current ERROR AMPLIFIER FB Input Bias Current COMP Source Current COMP Sink Current COMP High Clamp Voltage COMP Low Clamp Voltage GATE DRIVER TGATE Pull-Up Resistance TGATE Source Current TGATE Sink Resistance TGATE Sink Current BGATE Pull-Up Resistance BGATE Source Current BGATE Sink Resistance BGATE Sink Current Delay From TGATE Falling to BGATE Rising Delay From BGATE Falling to TGATE Rising BOOTSTRAP DIODE Forward Voltage Reverse Leakage POWER GOOD PGRSS PGRUV PGRSS PGOOD Pull Down Impedance PGRUV PGROV PGOOD = 5mA Sink; ISL8106CRZ PGOOD = 5mA Sink; ISL8106IRZ PGROC PGOOD = 5mA Sink; ISL8016CRZ PGOOD = 5mA Sink; ISL8106IRZ PGOOD Leakage Current PGOOD Maximum Sink Current IPGOOD PGOOD = 5V 50 45 25 22 63 63 32 32 <0.1 5.0 78 81 40 43 1.0 A mA PGOOD = 5mA Sink; ISL8106IRZ 67 95 118 PGOOD = 5mA Sink; ISL8106CRZ 75 95 115 VF IR PVCC = 5V, IF = 2mA VR = 25V 0.58 0.2 V A RTGATEPU 200mA Source Current (Note 3) 1.0 2.0 1.0 2.0 1.0 2.0 0.5 4.0 21 14 0.9 1.5 1.5 1.5 A A A A ns ns IFB ICOMPSRC ICOMPSNK VCOMPHC VCOMPLC FB = 0.60V FB = 0.40V, COMP = 3.20V FB = 0.80V, COMP = 0.30V FB = 0.40V, Sink 50A FB = 0.80V, Source 50A 3.10 0.09 20 2.5 0.3 3.40 0.15 3.65 0.21 nA mA mA V V VVO IVO VO = 0.60V VO = 3.30V FOSC = 300kHz; ISL8106CRZ FOSC = 300kHz; ISL8106IRZ 200 21 20 -10 -12 0.60 1.3 7.0 28 28 +10 +12 3.30 600 kHz kHz kHz % % V A A Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process, temperature, and line operating conditions. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ITGATESRC VTGATE to LX = 2.5V RTGATEPD 250mA Sink Current (Note 3) ITGATESNK VTGATE to LX = 2.5V RBGATEPU 250mA Source Current (Note 3) IBGATESRC VBGATE to PGND = 2.5V RBGATEPD 250mA Sink Current (Note 3) IBGATESNK VBGATE to PGND = 2.5V tTGATEFBG
ATER
tBGATEFTG
TGATE falling to BGATE rising BGATE falling to TGATE rising
ATER
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FN9283.1 November 10, 2006
ISL8106
Electrical Specifications
PARAMETER PGOOD Soft-Start Delay PROTECTION BSOC OCP Threshold Current BSOC Short-Circuit Threshold Current UVP Threshold Voltage OVP Rising Threshold Voltage OVP Falling Threshold Voltage OTP Rising Threshold Temperature OTP Temperature Hysteresis IOC ISL8106CRZ ISL8106IRZ ISC VUV VOVR VOVF TOTR TOTHYS (Note 3) (Note 3) 81 113 -33 -33 -26 -26 -50 84 116 103 150 25 87 119 -19 -17 A A A % % % C C Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process, temperature, and line operating conditions. SYMBOL TSS TEST CONDITIONS EN High to PGOOD High; ISL8106CRZ EN High to PGOOD High; ISL8106IRZ MIN 2.20 2.20 TYP 2.75 2.75 MAX 3.30 3.50 UNIT ms ms
Functional Pin Descriptions
GND (Bottom terminal pad)
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin, not the PGND pin. Connect the GND pad of the ISL8106 to the signal ground layer of the pcb using at least five vias, for a robust thermal and electrical conduction path. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitors that is not in the return path of the inductor ripple current flowing through the output capacitors.
rising threshold voltage VCCTHR. When the EN pin is pulled below the falling threshold voltage VENTHF, PWM immediately stops and VCC decays below the POR falling threshold voltage VCCTHF, at which time the IC turns off.
COMP (Pin 5)
The COMP pin is the output of the control-loop error amplifier. Loop compensation components connect from the COMP pin to the FB pin.
FB (Pin 6)
The FB pin is the inverting input of the control loop error amplifier. The converter will regulate to 600mV at the FB pin with respect to the GND pin. Scale the desired output voltage to 600mV with a voltage divider network made from resistors RTOP and RBOTTOM. Loop compensation components connect from the FB pin to the COMP pin.
VIN (Pin 1)
The VIN pin measures the converter input voltage with respect to the GND pin. VIN is a required input to the R3 PWM modulator. The VIN pin is also the input source for the integrated +5V LDO regulator.
FSET (Pin 7)
The FSET pin programs the PWM switching frequency of the converter. Connect a resistor RFSET and a 10nF capacitor CFSET from the FSET pin to the GND pin.
VCC (Pin 2)
The VCC pin is the output of the integrated +5V LDO regulator, which provides the bias voltage for the IC. The VCC pin delivers regulated +5V whenever the EN pin is pulled above VENTHR. For best performance, the LDO requires at least a 1F MLCC decouple capacitor to the GND pin.
VO (Pin 8)
The VO pin makes a direct measurement of the converter output voltage used exclusively by the R3 PWM modulator. The VO pin should be connected to the top of feedback resistor RTOP at the converter output. Refer to Typical Application Schematic.
FCCM (Pin 3)
The FCCM pin configures the controller to operate in forcedcontinuous-conduction-mode (FCCM) or diode-emulationmode (DEM). DEM is disabled when the FCCM pin is pulled above the rising threshold voltage VFCCMTHR, and DEM is enabled when the FCCM pin is pulled below the falling threshold voltage VFCCMTHF.
BSOC (Pin 9)
The BSOC pin is the input to the overcurrent protection (OCP) and short-circuit protection (SCP) circuits. Connect a resistor RBSOC between the BSOC pin and the LX pin. Select the value of RBSOC that will force the BSOC pin to source the IBSOC threshold current IOC when the peak inductor current reaches the desired OCP setpoint. The SCP threshold current ISC is fixed at twice the OCP threshold current IOC.
EN (Pin 4)
The EN pin is the on/off switch of the IC. When the EN pin is pulled above the rising threshold voltage VENTHR, VCC will ramp up and begin regulation. The soft-start sequence begins once VCC ramps above the power-on reset (POR)
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ISL8106
PGND (Pin 10)
The PGND pin should be connected to the source of the bottom-side MOSFET, preferably with an isolated path that is in parallel with the trace connecting the BGATE pin to the gate of the MOSFET. The PGND pin is an isolated path used exclusively to conduct the turn-off transient current that flows out the PGND pin, through the gate-source capacitance of the bottom-side MOSFET, into the BGATE pin, and back to the PGND pin through the pull-down resistance of the BGATE driver. The adaptive shoot-through protection circuit, measures the bottom-side MOSFET gate voltage with respect to the PGND pin, not the GND pin. the bottom-side MOSFET drain voltage for the diode emulation function. Connect the LX pin to the node consisting of the top-side MOSFET source, the bottom-side MOSFET drain, and the output inductor. Refer to Typical Application Schematic. This trace should be short, and positioned away from other weak signal traces. The parasitic capacitance and parasitic inductance of the LX node should be kept very low to minimize ringing. If ringing is excessive, it could easily affect current sample information. It would be best to limit the size of the LX node copper in strict accordance with the current and thermal management of the application.
BGATE (Pin 11)
The BGATE pin is the output of the bottom-side MOSFET gate driver. Connect to the gate of the bottom-side MOSFET. The signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. Route this trace in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces. There should be no other weak signal traces in parallel with these traces on any layer.
PGOOD (Pin 16)
The PGOOD pin is an open-drain output that is high impedance when the converter is in regulation, or when the EN pin is pulled below the falling threshold voltage VENTHF. The PGOOD pin has three distinct pull-down impedances that correspond to an OVP fault, OCP/SCP, or UVP and softstart. Connect the PGOOD pin to +5V through a pull-up resistor.
Functional Description
POR and Soft-Start
The power-on reset (POR) circuit monitors VCC for the VCCR (rising) and VCCF (falling) voltage thresholds. The purpose of soft-start is to limit the inrush current through the output capacitors when the converter first turns on. The PWM soft-start sequence initializes once VCC rises above the VCCR threshold, beginning from below the VCCF threshold. The ISL8106 uses a digital soft-start circuit to ramp the output voltage of the converter to the programmed regulation setpoint in approximately 1.5ms. The converter regulates to 600mV at the FB pin with respect to the GND pin. During soft-start a digitally derived voltage reference forces the converter to regulate from 0V to 600mV at the FB pin. When the EN pin is pulled above the rising EN threshold voltage VENTHR the PGOOD Soft-Start Delay TSS begins and the output voltage begins to rise. The output voltage enters regulation in approximately 1.5ms and the PGOOD pin goes to high impedance once TSS has elapsed. When the EN pin is pulled below the VENF threshold, the LDO stops regulating and PWM immediately stops, regardless of the falling VCC voltage. The soft-start sequence can be reinitialized and fault latches reset, once VCC falls below the VCCF threshold.
PVCC (Pin 12)
The PVCC pin is the input voltage for the bottom-side MOSFET gate driver BGATE. Connect a +5V power source to the PVCC pin with respect to the GND pin, a 1F MLCC bypass capacitor needs to be connected from the PVCC pin to the PGND pin, not the GND pin. The VCC output may be used for the PVCC input voltage source. Connect the VCC pin to the PVCC pin through a low-pass filter consisting of a resistor and the PVCC bypass capacitor. Refer to Typical Application Schematic.
BOOT (Pin 13)
The BOOT pin stores the input voltage for the top-side MOSFET gate driver. Connect an MLCC capacitor across the BOOT and LX pins. The boot capacitor is charged through an internal boot diode connected from the PVCC pin to the BOOT pin, each time the LX pin drops below PVCC minus the voltage dropped across the internal boot diode.
TGATE (Pin 14)
The TGATE pin is the output of the top-side MOSFET gate driver. Connect to the gate of the top-side MOSFET. The signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. Route this trace in parallel with the trace from the LX pin. These two traces should be short, wide, and away from other traces. There should be no other weak signal traces in parallel with these traces on any layer.
LX (Pin 15)
The LX pin is the return current path for the TGATE MOSFET driver. The LX pin also measures the polarity of
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FN9283.1 November 10, 2006
ISL8106
can simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The term "Ripple" in the name "Robust-RippleRegulator" refers to the converter output inductor ripple current, not the converter output ripple voltage. The output voltage is regulated to 600mV at the FB pin with respect to the GND pin. The FB pin is the inverting input of the error amplifier. The frequency response of the feedback control loop is tuned with a type-two compensation network connected across the FB pin and COMP pin.
2.75ms
EN
VOUT 1.5ms PGOOD
FIGURE 1. SOFT-START SEQUENCE
PGOOD
The PGOOD pin connects to three open drain MOSFETS each of which has a different rDS(ON). The PGOOD pin is an undefined impedance if VCC has not reached the rising POR threshold VCCR, or if VCC is below the falling POR threshold VCCF. The ISL8106 features a unique fault-identification capability that can drastically reduce trouble-shooting time and effort. The pull-down resistance of the PGOOD pin corresponds to the fault status of the controller. During softstart or if an undervoltage fault occurs, the PGOOD pulldown resistance is 95, or 30 for an overcurrent fault, or 60 for an overvoltage fault.
TABLE 1. PGOOD PULL-DOWN RESISTANCE CONDITION IC Off Soft-Start Undervoltage Fault Overvoltage Fault Overcurrent Fault PGOOD RESISTANCE Open 95 95 60 30
The R3 modulator synthesizes an AC signal VR, which is an ideal representation of the output inductor ripple current. The duty-cycle of VR is derived from the voltage measured at the VIN pin and VO pin with respect to the GND pin. Transconductance amplifiers convert the VIN and VO voltages into currents that charge and discharge the ripple capacitor CR. The positive slope of VR can be written as:
V RPOS = ( gm ) * ( V IN - V O ) (EQ. 1)
The negative slope of VR can be written as:
V RNEG = gm * V O (EQ. 2)
A voltage VW is referenced with respect to the error amplifier output voltage VCOMP, creating a window-voltage envelope into which voltage VR is compared. The VR, VCOMP, and VW signals feed into a hysteretic window comparator in which VCOMP is the lower threshold voltage and VW is the higher threshold voltage. PWM pulses are generated as VR traverses the VW and VCOMP thresholds. The charging and discharging rates of capacitor CR determine the PWM switching frequency for a given amplitude of VW with respect to VCOMP. The R3 regulator simultaneously affects switching frequency and duty cycle because it modulates both edges of the PWM pulses.
LDO
Voltage applied to the VIN pin with respect to the GND pin is regulated to +5VDC by an internal low-dropout voltage regulator (LDO). The output of the LDO is called VCC, which is the bias voltage used by the IC internal circuitry. The LDO output is routed to the VCC pin and requires a ceramic capacitor connected to the GND pin to stabilize the LDO and to decouple load transients. When the EN pin rises above the VENR threshold, VCC will turn on and rise to its regulation voltage. The LDO regulates VCC by pulling up towards the voltage at the VIN pin; the LDO has no pull-down capability.
Ripple Capacitor Voltage CR Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
Pulse Width Modulator
The ISL8106 is a hybrid of fixed frequency PWM control, and variable frequency hysteretic control. Intersil's R3 technology
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
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FN9283.1 November 10, 2006
ISL8106 MOSFET Gate-Drivers
The ISL8106 has internal gate-drivers for the top-side and bottom-side N-Channel MOSFETs. The bottom-side gatedriver is optimized for low duty-cycle applications where the bottom-side MOSFET conduction losses are dominant, requiring a low rDS(on) MOSFET. The BGATE pulldown resistance is small in order to clamp the gate of the MOSFET below the VGS(th) at turnoff. The current transient through the gate at turnoff can be considerable because the switching charge of a low rDS(on) MOSFET can be large. Both drivers incorporate bottom-side MOSFETS from conducting simultaneously and shorting the input supply. During turn-off of the bottom-side MOSFET, the BGATE to PGND voltage is monitored until it reaches a 1V threshold, at which time the TGATE driver is allowed to switch. During turn-off of the top-side MOSFET, the TGATE to LX voltage is monitored until it reaches a 1V threshold, at which time the BGATE driver is allowed to switch. The input power for the BGATE driver circuit is sourced directly from the PVCC pin. The input power for the TGATE driver circuit is sourced from a "boot" capacitor connected from the BOOT pin to the LX pin. The boot capacitor is charged from a 5V bias supply through a internal Schottky diode each time the bottom-side MOSFET turns on. rectifier, switching the bottom-side MOSFET regardless of the polarity of the output inductor current. In DEM, the bottom-side MOSFET is disabled during negative current flow from the output inductor. DEM is permitted when the FCCM pin is pulled low, and disabled when pulled high. When DEM is permitted, the converter will automatically select FCCM or DEM according to load conditions. If positive LX pin voltage is measured for eight consecutive PWM pulses, then the converter will enter diode-emulation mode on the next PWM cycle. If a negative LX pin voltage is measured, the converter will exit DEM on the following PWM pulse. An audio filter is incorporated into the PWM generation circuitry that prevents the switching frequency from entering the audible spectrum at low load conditions.
Overcurrent and Short-Circuit Protection
When an OCP or SCP fault is detected, the ISL8106 overcurrent and short-circuit protection circuit will pull the PGOOD pin low and latch off the converter. The fault will remain latched until the EN pin is pulled below VENF or if the voltage at the VIN pin is reduced to the extent that VCC has fallen below the POR VCCF threshold. Selecting the appropriate value of resistor RBSOC that is connected from the BSOC pin to the drain terminal of the bottom-side MOSFET to programs the OCP threshold. The OCP circuit measures positive-flowing, peak-current through the output inductor, not the DC current flowing from the converter to the load. The bottom-side MOSFET drain current is assumed to be equal to the positive output inductor current when the top-side MOSFET is turn off. Current briefly conducts through the bottom-side MOSFET body diode until the BGATE driver goes high. The peak inductor current develops a voltage across the rDS(ON) of the bottom-side MOSFET just as if it were a discrete currentsense resistor. An OCP fault will occur when the BSOC pin has measured more than the OCP threshold current IOC, on consecutive PWM pulses, for a period exceeding 20s. It does not matter how many PWM pulses are measured during the 20s period. If a measurement falls below IOC before 20s has elapsed, then the timer is reset to zero. An SCP fault will occur when the BSOC pin has measured more than the short-circuit threshold current ISC, in less than 10s, on consecutive PWM pulses. The relationship between ID and IBSOC can be written as:
I BSOC * R BSOC = I D * r DS ( ON ) (EQ. 3)
TGATE
50%
BGATE
tBGFTGR tTGFBGR
50%
FIGURE 3. GATE DRIVE TIMING DIAGRAM
Diode Emulation
Positive inductor current can flow from the source of the topside MOSFET or from the drain of the bottom-side MOSFET. Negative inductor current flows into the drain of the bottomside MOSFET. When the bottom-side MOSFET conducts positive inductor current, the LX voltage will be negative with respect to the GND pin. Conversely, when the bottom-side MOSFET conducts negative inductor current, the LX voltage will be positive with respect to the GND pin. Negative inductor current occurs when the output load current is less than 1/2 the inductor ripple current. The ISL8106 can be configured to operate in forcedcontinuous-conduction-mode (FCCM) or in diode-emulationmode (DEM), which can improve light-load efficiency. In FCCM, the controller always operates as a synchronous
The value of RBSOC can then be written as:
I PP I FL + -------- * OC SP * r DS ( ON ) 2 R BSOC = ---------------------------------------------------------------------------I OC (EQ. 4)
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ISL8106
Where: - RBSOC () is the resistor used to program the overcurrent setpoint - IBSOC is the current sense current that is sourced from the BSOC pin - IOC is the IBSOC threshold current value sourced from the BSOC pin that will activate the OCP circuit - IFL is the maximum continuous DC load current - IPP is the inductor peak-to-peak ripple current - OCSP is the desired overcurrent setpoint expressed as a multiplier relative to IFL low. If the EN pin is pulled below VENF or if the voltage at the VIN is reduced to the extent that VCC has fallen below the POR VCCF threshold, normal operation will resume however, the temperature hysteresis TOTHYS is reset.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. A multi-layer printed circuit board is recommended. Figure 4 shows the critical components of the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage
VCC CBP_PVCC PVCC CBP_VCC VIN RVCC
Overvoltage
When an OVP fault is detected, the ISL8106 overvoltage protection circuit will pull the PGOOD pin low and latch off the converter. The fault will remain latched until the EN pin is pulled below VENF or if the voltage at the VIN pin is reduced to the extent that VCC has fallen below the POR VCCF threshold. When the voltage at the FB pin (relative to the GND pin) has exceeded the rising overvoltage threshold VOVR, the converter will latch off; however, the BGATE driver output will stay high, forcing the bottom-side MOSFET to pull down the output voltage of the converter. The bottom-side MOSFET will continue to pull down the output voltage until the voltage at the FB pin relative to the GND pin, has decayed below the falling overvoltage threshold VOVF, at which time the BGATE driver output is driven low, forcing the bottom-side MOSFET off. The BGATE driver output will continue to switch on at VOVR and switch off at VOVF until the EN pin is pulled below VENF or if the voltage at the VIN is reduced to the extent that VCC has fallen below the POR VCCF threshold.
ISL8106
CIN TGATE BOOT CIN LX COUT BGATE PGND GND Q2 LOAD
FN9283.1 November 10, 2006
UnderVoltage
When an UVP fault is detected, the ISL8106 undervoltage protection circuit will pull the PGOOD pin low and latch off the converter. The UVP fault occurs when the voltage at the FB pin relative to the GND pin, has fallen below the undervoltage threshold VUV. The fault will remain latched until the EN pin is pulled below VENF or if the voltage at the VIN is reduced to the extent that VCC has fallen below the POR VCCF threshold.
Q1
LOUT
VOUT
Over-Temperature
When an OTP fault is detected, the ISL8106 overtemperature protection circuit suspends PWM, but will not affect the PGOOD pin, or latch off the converter. The overtemperature protection circuit measures the temperature of the silicon and activates when the rising threshold temperature TOTR has been exceeded. The PWM remains suspended until the silicon temperature falls below the temperature hysteresis TOTHYS at which time normal operation is resumed. All other protection circuits will function normally during OTP however, since PWM is inhibited, it is likely that the converter will immediately experience an undervoltage fault, latch off, and pull PGOOD 10
KEY TRACE SIZED FOR 4A PEAK CURRENT SHORT TRACE, MINIMUM IMPEDANCE ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
ISL8106
levels. Keep the metal runs from the LX terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the LX nodes. Use the remaining printed circuit layers for small signal wiring. Locate the ISL8106 within 2 to 3 inches of the MOSFETs, Q1 and Q2 (1 inch or less for 500kHz or higher operation). The circuit traces for the MOSFETs' gate and source connections from the ISL8106 must be sized to handle up to 4A peak current. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT pin and the phase node. Where: - FOSC is the PWM switching frequency. - RFSET is the FOSC programming resistor. - 60 x [1 x 10-12] is a constant.
Selection of the LC Output Filter
The duty cycle of a buck converter is ideally a function of the input voltage and the output voltage. This relationship can be written as:
V OUT D ( V IN ) = --------------V IN (EQ. 9)
Where: - D is the PWM duty cycle. - VIN is the input voltage to be converted. - VOUT is the regulated output voltage of the converter. The output inductor peak-to-peak ripple current can be written as:
V OUT * [ 1 - D ( V IN ) ] I PP = ---------------------------------------------------F OSC * L O (EQ. 10)
Programming the Output Voltage
When the converter is in regulation there will be 600mV from the FB pin to the GND pin. Connect a two-resistor voltage divider across the VO pin and the GND pin with the output node connected to the FB pin. Scale the voltage-divider network such that the FB pin is 600mV with respect to the GND pin when the converter is regulating at the desired output voltage. Programming the output voltage can be written as:
R BOTTOM V REF = V OUT * -------------------------------------------------R TOP + R BOTTOM (EQ. 5)
Where: IPP is the peak-to-peak output inductor ripple current. FOSC is the PWM switching frequency. LO is the nominal value of the output inductor.
Where: - VOUT is the desired output voltage of the converter. - VREF is the voltage that the converter regulates to at the FB pin. - RTOP is the voltage-programming resistor that connects from the FB pin to the VO pin. It is usually chosen to set the gain of the control-loop error amplifier. It follows that RBOTTOM will be calculated based upon the already selected value of RTOP. - RBOTTOM is the voltage-programming resistor that connects from the FB pin to the GND pin. Calculating the value of RBOTTOM can now be written as:
V REF * R TOP R BOTTOM = -----------------------------------V OUT - V REF (EQ. 6)
A typical step-down DC/DC converter will have an IPP of 20% to 40% of the nominal DC output load current. The value of IPP is selected based upon several criteria such as MOSFET switching loss, inductor core loss, and the resistance the inductor winding, DCR. The DC copper loss of the inductor can be estimated by:
P COPPER = [ I LOAD ] 2 * DCR (EQ. 11)
The inductor copper loss can be significant in the total system power loss. Attention has to be given to the DCR selection. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. A saturated inductor could cause destruction of circuit components, as well as nuisance OCP faults. A DC/DC buck regulator must have output capacitance CO into which ripple current IPP can flow. Current IPP develops a corresponding ripple voltage VPP across CO, which is the sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of the capacitor. These two voltages can be written as:
V ESR = I PP * E SR (EQ. 12)
Programming the PWM Switching Frequency
The PWM switching frequency FOSC is programmed by the resistor RFSET that is connected from the FSET pin to the GND pin. Programming the approximate PWM switching frequency can be written as:
1 F OSC = -------------------------------------------------------------- 12 60 * R FSET * [ 1 x 10 ] (EQ. 7)
and
I PP V C = ---------------------------------8 * CO * F
OSC
Estimating the value of RFSET can now be written as:
1 R FSET = ------------------------------------------------------- 12 60 * F OSC * [ 1 x10 ] (EQ. 8)
(EQ. 13)
If the output of the converter has to support a load with high pulsating current, several capacitors will need to be 11
FN9283.1 November 10, 2006
ISL8106
paralleled to adjust the ESR to achieve the required VPP. The inductance of the capacitor can cause a brief voltage dip when the load transient has an extremely high slew rate. Low inductance capacitors constructed with reverse package geometry are available. A capacitor dissipates heat as a function of RMS current. Be sure that IPP is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current. Take into account that the specified value of a capacitor can drop as much as 50% as the DC voltage across it increases. In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain terminal of the top-side MOSFET and the source terminal of the bottom-side MOSFET, in order to reduce the voltage ringing created by the switching current across parasitic circuit elements.
MOSFET Selection and Considerations
Typically, MOSFETS cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. The MOSFETS used in the power conversion stage of the converter should have a maximum VDS rating that exceeds the upper voltage tolerance of the input power source, and the voltage spike that occurs when the MOSFET switches off. Placing a low ESR ceramic capacitor as close as practical across the drain of the top-side MOSFET and the source of the bottom-side MOSFET will reduce the amplitude of the turn-off voltage spike. The MOSFET input capacitance CISS, and on-state drain to source resistance rDS(ON), are to an extent, inversely related; reduction of rDS(ON) typically results in an increase of CISS. These two parameters affect the efficiency of the converter in different ways. The rDS(ON) affects the power loss when the MOSFET is completely turned on and conducting current. The CISS affects the power loss when the MOSFET is actively switching. Switching time increases as CISS increases. When the MOSFET switches it will briefly conduct current while the drain to source voltage is still present. The power dissipation during this time is substantial so it must be kept as short as practical. Often the top-side MOSFET and the bottom-side MOSFET are different devices due to the trade-offs that have to be made between CISS and rDS(ON). The bottom-side MOSFET power loss is dominated by rDS(ON) because it conducts current for the majority of the PWM switching cycle; the rDS(ON) should be small. The switching loss is small for the bottom-side MOSFET even though CISS is large due to the low rDS(ON) of the device, because the drain to source voltage is clamped by the body diode. The top-side MOSFET power loss is dominated by CISS because it conducts current for the minority of the PWM switching cycle; the CISS should be small. The switching loss of the top-side MOSFET is large compared to the bottom-side MOSFET because the drain to source voltage is not clamped. For the bottom-side MOSFET, its power loss can be assumed to be the conduction loss only and can be written as:
P CONBS D ( V IN ) [ I LOAD ]
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. Figure 5 is a graph of the input RMS ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. The ripple current calculation is written as:
2 2 2D ( I MAX ( D - D ) ) + x I MAX ----- 12 I IN_RMS = ---------------------------------------------------------------------------------------------------I MAX
(EQ. 14)
Where: - IMAX is the maximum continuous ILOAD of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as:
V OUT D = ------------------------V IN EFF
NORMALIZED INPUT RMS RIPPLE CURRENT
0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0
x=1 x = 0.75 x = 0.50 x = 0.25 x=0
2
*
r DS ( ON )BS * [ 1 - D ( V IN ) ]
(EQ. 15)
For the top-side MOSFET, its conduction loss can be written as:
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
P CONTS D ( V IN ) = [ I LOAD ]
2
*
r DS ( ON )TS * D ( V IN )
(EQ. 16)
DUTY CYCLE
FIGURE 5. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
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FN9283.1 November 10, 2006
ISL8106
For the top-side MOSFET, its switching loss can be written as:
V IN * I VAL * T ON * F V IN * I PEAK * T OFF * F OSC OSC P SWTS ( V IN ) = ------------------------------------------------------------ + -------------------------------------------------------------------2 2 (EQ. 17)
The peak and valley current of the inductor can be obtained based on the inductor peak-to-peak current and the load current. The turn-on and turn-off time can be estimated with the given gate driver parameters in the Electrical Specification Table.
Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage is regulated to the reference voltage level. The error amplifier output is compared with the oscillator triangle wave to provide a pulse-width modulated wave with an amplitude of VIN at the LX node. The PWM wave is smoothed by the output filter. The output filter capacitor bank's equivalent series resistance is represented by the series resistor ESR.
CCOMP1
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor can be written as:
Qg C BOOT = ----------------------V BOOT (EQ. 18)
RCOMP CCOMP2 RTOP FB
COMP
Where:
EA
+
REF
- Qg is the total gate charge required to switch the topside MOSFET - VBOOT, is the maximum allowed voltage decay across the boot capacitor each time the MOSFET is switched on As an example, suppose the top-side MOSFET has a total gate charge QG, of 25nC at VGS = 5V, and a VBOOT of 200mV. The calculated bootstrap capacitance is 0.125F; select at least the first standard component value of greater capacitance than calculated, that being 0.15F. Use an X7R or X5R ceramic capacitor.
RBOTTOM
VO
R3 Modulator FSET RFSET CFSET
Compensating the Converter
The LC output filter has a double pole at its resonant frequency that causes the phase to abruptly roll downward. The R3 modulator used in the ISL8106 makes the LC output filter resemble a first order system in which the closed loop stability can be achieved with a Type II compensation network.
CCOMP1 QTOP_SIDE TGATE CCOMP2 RCOMP Gate Drivers RTOP FB - ERROR AMPLIFIER + ISL8106 COMP GND BGATE ESR LX LOUT DCR
VIN
VIN
QBOTTOM_SIDE COUT
VREF
FIGURE 6. SYSTEM CONTROL BLOCK DIAGRAM FIGURE 7. COMPENSATION REFERENCE CIRCUIT
13
FN9283.1 November 10, 2006
ISL8106
The control loop model of the ISL8106 is partitioned into function blocks consisting of: - The duty cycle to Vo transfer function GVD(s) which is determined by the value of the output power components, input voltage, and output voltage. - The Vcomp to duty cycle transfer function Fm(s) which is determined by the PWM frequency, input voltage, output voltage, resistor RFSET, and capacitor CFSET. - The product of the GVD(s) and Fm(s) transfer functions is expressed as the VCOMP to Vo transfer function GVOVC(s). - The type-two compensation network GCOMP(s) that connects across the COMP and FB pins. - The product of the GCOMP(s) and GVOVC(s) transfer functions is expressed as the loop transfer function T(s).
T(s)=GCOMP(s) x GVOVC(s)
120
Vcomp to Vo Transfer Function Gvovc(s)
120 100 80 90 60 30
Gain (db)
40 20 0 20 40 10 100 1 .10
3
30 60 90 120 1 .10
4
1 .10
5
1 .10
6
150
Frequency (Hz) Gain (Gvovc) Phase (Gvovc)
FIGURE 9. OPEN LOOP TRANSFER FUNCTION
Voltage Loop Gain T(s)
90 75 60
VREF + - GCOMP(s)
VCOMP GVOVC(s)
Vo
100 80
Gain (db)
40 20 0 20 40 10 100 1 .10
3
30 15 0 15 1 .10
4
FIGURE 8. SYSTEM CONTROL BLOCK DIAGRAM
The compensator transfer function can be written as:
s i * 1 + -------- z1 G COMP ( s ) = ---------------------------------s s * 1 + -------- p1
1 .10
5
1 .10
6
30
Frequency (Hz)
(EQ. 19)
Gain (Tv) Phase (Tv)
where the compensator zero fz1 is
1 z1 = ------------------------------------------------R COMP * C COMP2 z1 f z1 = --------2* (EQ. 20)
FIGURE 10. CLOSED LOOP TRANSFER FUNCTION
(EQ. 21)
the compensator pole fp1 is
1 1 p1 = ------------------------ + -----------------------C COMP1 C COMP2 p1 f p1 = --------2*
*
1 -------------------R COMP
(EQ. 22)
(EQ. 23)
and
1 i = ------------------------------------------------------------------------------------R COMP * [ C COMP1 + C COMP2 ] (EQ. 24)
The Your local Intersil representative can provide a PCbased tool that can be used to calculate compensation network component values and help simulate the loop frequency response. The compensation network consists of the internal error amplifier of the ISL8106 and the external components RTOP, RCOMP, CCOMP1, and CCOMP2 as well as the frequency setting components RFSET, and CFSET, are identified in the schematic Figure 7.
14
FN9283.1 November 10, 2006
Phase
60
45
Phase
60
0
ISL8106 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.50 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerances conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN9283.1 November 10, 2006

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